HMC700LP4E【PDF 9/26 页】IC FRACT-N PLL 16BIT 24QFN

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Sheet目录1996

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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com

Application Support: apps@hittite.com

L-

0 - 17

HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Figure 15. Serial Port Timing Diagram - Write Serial Port WRITE Operation

Serial Port READ Operation

a typical rEaD cycle is shown in Figure 16.

a. the Master (host) asserts both SEn (Serial Port Enable) and SDi to indicate a rEaD cycle, followed

by a rising edge ScK. note: the Lock Detect function is multiplexed onto the LD_SDo pin. it is

suggested that lock detect (LD) only be considered valid when SEn is low. in fact LD will not toggle

until the first active data bit toggles on LD_SDo, and will be restored immediately after the trailing

edge of the LSB of serial data out as shown in Figure 15.

b. the slave (synthesizer) reads SDi on the 1st rising edge of ScK after SEn. SDi high initiates the

rEaD cycle (rD).

c. Host places the six address bits on the next six falling edges of ScK, MSB first.

d. Slave registers the address bits on the next six rising edges of ScK (2-7).

e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDo on the next 24

rising edges of ScK (8-31), MSB first .

f. Host registers the data bits on the next 24 falling edges of ScK (8-31).

g. Slave restores Lock Detect on the 32nd rising edge of ScK.

h. SEn is de-asserted on the 32nd falling edge of ScK.

i. the 32nd falling edge of ScK completes the rEaD cycle.

Figure 16. Serial Port Timing Diagram - READ Serial Port Operation

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